1. Field of the Invention
The present invention relates to an advanced microcontroller bus architecture (AMBA) bus system of an system-on-chip (SOC) and in particular to a method of generating a strobe signal of a peripheral device.
2. Description of the Related Art
The Advanced Microcontroller Bus Architecture bus specification, introduced by ARM, Ltd., is an open-standard bus specification that includes a method of coupling function blocks, such as a central processing unit (CPU) of an SOC, or a digital signal processor (DSP), and a method of managing the function blocks.
The AMBA bus specification defines a common system bus, i.e., backbone, for internal modules of the SOC, and enhances efficiency of the system design.
The AMBA bus specification includes the advanced high-performance bus (AHB), the advanced system bus (ASB) and the advanced peripheral bus (APB).
FIG. 1 is a block diagram illustrating a conventional AMBA bus system.
Referring to FIG. 1, the AMBA bus system includes an external memory interface 10, an ARM processor 12, an on-chip random-access memory (RAM) 14, a direct memory access (DMA) bus master 16, a main bus 20, a bridge 30, a peripheral bus 50, and peripheral devices, such as a universal asynchronous receiver/transmitter (UART) 40, a timer 42, a keypad 44, and a programmed input/output (PIO) 46.
The main bus 20 employs the AHB or the ASB, and couples the ARM processor 12, the on-chip memory 14 and the DMA bus master 16.
The AHB and the ASB are high-performance buses that provide pipeline operation, burst operation, and multiple bus masters.
The peripheral bus 50 employs the APB, and couples the UART 40, the timer 42, the keypad 44 and the PIO 46.
The APB is characterized by low power consumption and control of latched addresses, and provides a simple interface between the peripheral devices.
The bridge 30 as a bus master controls data transfer between system devices coupled to the main bus 20 and the peripheral devices coupled to the peripheral bus 50.
FIG. 2 is a block diagram illustrating signal transfer between the bus master (or bridge) and the peripheral devices according to the conventional bus system shown in FIG. 1.
Referring to FIG. 2, the bus master 30 is synchronized to a clock signal PCLK to provide to the peripheral devices a plurality of selection signals PSEL1 through PSELn for selecting the peripheral devices such as the UART 40, the timer 42, the keypad 44 and the PIO 46; a strobe signal PENABLE for controlling input/output of all of the peripheral devices; an address signal PADDR for indicating a location of a register used for storing data; and a plurality of control signals such as a read/write mode control signal PWRITE.
In addition, the bus master 30 transmits/receives write data PWDATA with the corresponding control signal during a write mode to/from the peripheral devices, and read data PRDATA with the corresponding control signal during a read mode to/from the peripheral devices.
That is, the peripheral device selected by the corresponding selection signal transmits/receives, according to an operation mode, the read data PRDATA and the write data PWDATA in response to the control signals provided through the bus master 30.
FIG. 3 is a timing diagram illustrating an operation of the bus system shown in FIG. 1 during a data read mode.
Referring to FIGS. 2 and 3, the bus master 30 generates a valid address signal PADDR, a read/write mode control signal PWRITE, and a selection signal PSEL at a second clock cycle T2, and the bus master 30 generates a strobe signal PENABLE at a third clock cycle T3.
By an activation of the strobe signal PENABLE, read data PRDATA outputted from the selected peripheral device are transmitted to the bus master 30, and the bus master 30 reads the read data PRDATA at a fourth clock cycle T4.
In the timing diagram shown in FIG. 3, the address signal PADDR, the read/write mode control signal PWRITE and the selection signal PSEL are provided stably for two cycles before the read data PRDATA are inputted to the bus master 30; thus, these control signals do not affect data transmission delay through the peripheral bus 50.
The data transmission delay is actually affected by the strobe signal PENABLE. Because the strobe signal PENABLE generated by the bus master 30 is commonly inputted to all of the peripheral devices based on the APB bus protocol, a high fan-out capability is required, and because some peripheral devices may be far from the bus master 30, a path length to a remote peripheral device becomes long. As a result, the strobe signal PENABLE causes the prolonged data transmission delay due to the high fan-out capability requirement and the long path length.
In the timing diagram shown in FIG. 3, the reference symbol ‘t1’ represents a delay time during which the strobe signal PENABLE is transmitted to one of the peripheral devices from the bus master 30.
The reference symbol ‘t2’ represents a set-up time period required beforehand in order that the bus master 30 may read valid data during a fourth clock cycle T4, and the set-up time period t2 is decreased by an amount as much as the delay time t1.
Because the delayed strobe signal PENABLE also delays data transfer through the peripheral bus 50, a critical path of an entire system is formed to limit a maximum operating frequency.
Further, as size of the SOC increases and operating frequency becomes higher, the delay time resulting from the strobe signal PENABLE decreases efficiency of the entire system.